Since the early 1970s, a new generation of dynamic random access memory (DRAM) circuits has been developed approximately every four years. Each generation has been characterized by a four-fold density increase over the preceding generation. This has been accomplished by using photolithographic processes of ever greater resolution, by designing the individual memory cells so that the cell capacitor stores charge vertically rather than horizontally, and by maintaining sufficient cell capacitance through the use of high-performance cell dielectrics and three-dimensional capacitor structures. Thus, a cell in each new DRAM generation takes up less chip real estate than those of former generations.
The minimum size of features and spaces that a given piece of photolithographic equipment can produce is directly related to its resolution capability. The sum of minimum feature width (F) and minimum space width (S) producible with a given piece of photolithographic equipment is generally referred to as "minimum pitch". Since, for practical purposes, F can be considered to be equal to S, minimum pitch is, therefore, approximately equal to double the minimum feature width, or 2F. Using contemporary photolithography techniques, one minimum-width line (feature) and one minimum-width space may be defined for a given minimum pitch.
In a contemporary DRAM cell having conventional folded digit line architecture, at least two word lines and two spaces between word lines (a total width of 4F) must be created within the X-direction width of a cell. In the Y-direction, a digit line and a space between digit lines are required. Thus, total cell area is 4F (the X-direction width) multiplied by 2F (the Y-direction width), or 8F.sup.2. Contemporary 16-megabit DRAMs are typically fabricated with photolithographic processes having 0.3-0.5 .mu.m minimum feature resolution. Thus, the area of an average 8F.sup.2 16-megabit DRAM cell is about 0.75-2.0 .mu.m.sup.2.
If all structures within a DRAM cell are constructed on top of one another, and a cross-point array is employed, then the absolute minimum size of a cell will be 2F by 2F, or 4F.sup.2. Although, the cross-point array architecture was abandoned at the 256-kilobyte generation by virtually all DRAM manufacturers due to the noise levels inherent in open digit line architecture normally associated with cross-point cell arrays, it may experience a renaissance due to the compact nature of the layout and new techniques for reducing variations in signal strength associated with the open digit line architecture. Although 4F.sup.2 DRAM cell designs have been suggested and patented, most (if not all) have required a cell structure having a trench capacitor, a vertical access transistor, and a digit line contact on top of the transistor. Most DRAM manufacturers have forsaken trench capacitors in favor of stacked capacitors because of capacitor leakage associated with crystal defects introduced into the substrate by the trenching operation. What is needed is a 4F.sup.2 cell design which incorporates a stacked capacitor.